STEC offers end-of-life and legacy modules to support older, previous generation products.

Many OEMs who have designed in what is now legacy or end-of-life memory technology are faced with a difficult challenge. How to support memory module replacements and upgrades for their end products, as the memory components needed to build the modules are being phased out are increasingly hard to find.

Even though these end products are no longer in production or are older generation products, they still require these legacy memory module technologies to maximize their performance and to function. Many systems still use older versions of memory technology such as FPM and EDO architectures for which STEC has an extensive library of readily available designs.

STEC will work with you to forecast and to plan for your long-term needs for these difficult to obtain products. Additionally, STEC's engineers and sales professionals look forward to working with you to design new memory technology into both existing and new product designs.

A page is described as the section of memory available within a row address. Within one specific row are several columns of memory bits. With Fast Page Mode (FPM) Memory Modules, you need only specify the row address once for accesses within the same page addresses. Successive accesses to the same page of memory only require a column address to be selected, which saves time in accessing the memory. JEDEC, the electronic standards agency, has specified standards for the FPM DRAM.

Extended Data Out DRAMs work very similar to FPM DRAMs. EDO DRAMs have the ability to work within a page like FPM DRAMs. The primary advantage with EDO DRAMs over FPM DRAMs is that EDO DRAMs hold the data valid even after the signal that "strobes" the column address goes inactive. This allows faster microprocessors to manage time more efficiently, performing many tasks without having to attend to slower memory. That is, while the EDO DRAM is retrieving an instruction for the microprocessor, the microprocessor can perform other tasks without worrying that the data will become invalid. JEDEC has specified standards for the EDO DRAM.