DDR SDRAM memory (Double Data Rate Synchronous Dynamic Random Access Memory) is the computer memory type in computer techniques. It replaced SDRAM memory.
This form of memory transfers data at twice quicker than traditional SDRAM memory. In other words, data transfer twice per cycle not only on the rising but on the falling edge of the clock signal. Due to this, the data rate doubles without increasing the clock frequency of the memory signal, i.e. the operation runs at the same clock frequency.
The main constraint element to increase the memory clock speed is a memory core (storage array). Besides this, there are storage buffers by which the memory core exchanges data with the memory bus. These buffers have higher speed and the memory clock frequency can be easily increased. This method is used in DDR memory.
In SDRAM the memory core and buffers operate synchronously at the same frequency while DDR-RAM transfers two bits per clock cycle. This mode of operation is possible if these two bits are available to the buffer IO at each memory cycle. Thus, two independent transmission lines from the memory core are used and bits come to the data bus in a desired order.
In order to synchronize the operation of the IO buffers and memory core, the same clock speed (the same timing pulse) is used. Only if the synchronization is run on the rising edge timing pulse, the positive and negative edge timing pulse in the input-output buffer for synchronization is used. Thus, the transmission of two bits in the input-output buffer for two separate lines is carried out on the rising edge timing pulse and the falling edge timing pulse. This provides more than twice as high speed of the buffer and twice of the memory bandwidth. And this fact can be considered as a great advantage because it increases the data rate and reduces such problems as the signal integrity requirements.
As the memory can provide a burst of data from 2, 4, 8 memory locations at a rate of 2 memory locations per clock cycle, the data is available after some memory latency.
Arrays and Banks of DDR SDRAM
Synchronous dynamic random access memory is consists of multiple arrays of single-bit storage sites that are arranged in a two-dimensional structure. This structure is formed by the intersection of individual rows and columns called banks. They provide memory space and allow the control process and other system components with direct access to main system memory to write and read data to and from a storage location.
Taking into account the memory origin and its differences, all other fundamental aspects of DDR-memory has not changed: the structure of several independent banks allows combining data from one sample bank with the address of another bank, it is possible to have two open pages at one time.
Let’s see how a four bank DDR SDRAM works.
– A row is opened by an activate command in the first bank.
– The second bank is activated in a second command.
– When the rows are open, the commands “Write” or “Read” should be sent to columns in the rows in banks.
– When these operations are completed, a precharge command is sent immediately that closes the row and open bank areas.
– The memory is ready for the next command.
DDR SDRAM Power
As DDR memory is becoming widely used for different applications that require fast processing of huge data amount, users want it to operate fast but it depends on the power. In turn, the power depends on the number of open rows. If you want to gain a fast operation, you should open a lot of rows together but this consumes more power. If you open one row in each bank, you’ll get low operation. Thus, when the clock rate increases, the power consumption also grows.