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With a
lack of standardization, write/erase cycle endurance for solid-state
storage is specified in many ways by the different flash vendors.
Some vendors use the physical flash block level to specify the
product's endurance, while others refer to logical block level,
or even drive level. In addition, endurance is also related
to data retention can be specified higher if the data retention
specification is lower. It is therefore better to compare all
the components that affect the endurance calculation and evaluate
those instead.
Flash endurance is based on what NAND flash technology is
used (SLC vs. MLC) and what the capabilities are of the flash
controller in terms of error correction, wear leveling algorithm,
bad block management, etc.
EDUCATION
Wear
Leveling
The individual blocks in a NAND flash device are limited
in the number of Program/Erase Cycles they can sustain
before the probability of errors rise to unacceptable
levels. It is therefore extremely important that all
blocks within a flash chip are aged in the same manner.
If one area gets written to more frequently, while another
never gets never touched, the lifetime of the entire
flash is impacted, even though some parts of the flash
were hardly ever used.
To overcome this limitation, a flash management algorithm
file system needs to be implemented to make sure that
with any new write operation, the youngest block is
used. STEC's implemented wear leveling scheme spreads
flash media usage evenly across all pages, thereby maximizing
flash lifetime.
Error
Correction/Detection
The implemented Error Correction algorithm in a flash
controller has a direct influence on the overall flash
endurance number. When a certain flash block has reached
its write/erase cycle limit, it will show a higher probability
of errors. By implementing a powerful ECC mechanism
that can detect and correct these errors with our advanced
ECC protocols that minimize byte errors per flash page
(512 bytes), STEC's flash controller can extend the
life of a flash block far beyond its original specification,
thereby extending the overall lifespan of the solid
state drive.
Bad
Block Management
When implementing flash management algorithms that
include a strong wear leveling and Error Correction
Mechanism, there is also a need for the management algorithm
to monitor and maintain bad blocks within the NAND device.
Many NAND-based products maintain tables of known bad
blocks, while STEC's management algorithm not only maintains
the existing bad block table, but also monitors the
device for new bad blocks during use. STEC can then
replace the new bad blocks and update all necessary
aspects of the data contained in spare blocks that are
reserved for use. This practice further enhances the
overall SSD lifespan.
Single Level Cell Flash (SLC) vs. Multi-Level Cell Flash (MLC)
Flash manufacturers specify a limit on how many write/erase
cycles can be performed on a given page before the signs
of wear-out become obvious and the probability of errors
rise to unacceptable levels. Today's generation of Single
Level Cell NAND Flash devices are guaranteed for 100,000
Program/Erase cycles per Erase Block with 1-bit ECC.
Multi Level Cell NAND flash devices are offered with
only 10,000 cycles. STEC is using solely SLC flash in
its solid-state storage products, since the reliability
and endurance is superior to MLC technology.
